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13 April 2016
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I2C Controller IP Cores & Reference Designs
Digital Blocks offers full protocol & timing compliant I2C Controller IP Verilog Cores, with releases containing Master/Slave, Master-only, and Slave-only functions.
I2C Controller Verilog IP Cores
The Master/Slave I2C Controller IP Cores (Verilog Cores DB-I2C-MS-APB, DB-I2C-MS-AHB, DB-I2C-MS-AXI, DB-I2C-MS-AVLN) contain a parameterized FIFO, Control Unit, & Interrupt Controller to fully off-load the I2C transfer from the processor. The full off-load capabilities target applications with higher performance algorithm requirements or minimal software development plans.
The Master-only I2C Controller IP Cores (Verilog Cores DB-I2C-M-APB, DB-I2C-M-AHB, DB-I2C-M-AXI, DB-I2C-M-AVLN) have the Master function from the Master/Slave releases, with parameterized FIFO, I2C Master Control Unit, & Interrupt Controller, to fully off-load the I2C transfers from the processor. The Master-only I2C Controller IP offers a smaller VLSI footprint.
The Slave-only I2C Controller IP Cores (Verilog Cores DB-I2C-S-APB, DB-I2C-S-AHB, DB-I2C-S-AXI, DB-I2C-S-AVLN) have the Slave function from the Master/Slave releases, with parameterized FIFO, I2C Slave Control Unit, & Interrupt Controller, to fully off-load the I2C transfers from the processor. The Slave-only I2C Controller IP offers a smaller VLSI footprint.
As a licensing option, Hs-mode can be included with the Master/Slave, Master-only, and Slave-only (Verilog Cores DB-I2C-MS-Hs-Mode, DB-I2C-M-Hs-Mode, DB-I2C-S-Hs-Mode) I2C Controller IP with any AMBA Interface. The Hs-mode licensing option offers full Hs-mode protocol, timing and electrical compliance to the Hs-mode I2C specification. With the following features, the Hs-Mode option offers the highest system-level I2C performance capability on the market: (1) 3.4 Mbit/s Hs-Mode transfer on the I2C Bus; (2) I2C Controller FIFO to hold blocks of data plus an off-load Finite State Machine to manage the transfers; (3) optional DMA controller to move data between the I2C Controller and System Memory or Registers (in addition to the processor having access to the FIFO).
Adding to the full feature Slave-only I2C Controller IP with AMBA Bus Interfaces to the processor, Digital Blocks offers Slave-only I2C Controllers with the external SCL as the clock source for the I2C logic (Verilog Cores DB-I2C-S-SCL-CLK and DB-I2C-S-SCL-CLK-APB). The DB-I2C-S-SCL-CLK is for configuring registers in ICs with low noise or power requirements while the DB-I2C-S-SCL-CLK-APB for interface to the CPU in ICs with low power requirements. Contact Digital Blocks with any additional unique low power I2C Slave Controllers requirements that you might have.
To learn more about the I2C Family of IP Cores Digital Blocks offers, including Master/Slave, Master-only and Slave-only IP Cores, as well as Interconnect fabrics for AMBA AXI & APB & AHB & Altera Avalon, please see the IP Cores page or contact Digital Blocks.
I2C Controller Reference Designs & Evaluations
Digital Blocks offers I2C Controller IP Core reference designs & evaluations that enable you to accelerate the design-in of an I2C Bus within your system.
For FPGA design teams, we offer AMBA Interfaces to CPUs in all Master/Slave, Master-only, and Slave-only releases. For Altera® FPGAs, we additionally offer the Avalon Interface to the Nios® II embedded processor. All I2C Controller IP Cores are available in Verilog RTL or, for lower costs, Altera® or Xilinx® netlist formats.
For ASIC, ASSP, Custom IC design teams, we offer AMBA Interfaces to CPUs in all Master/Slave, Master-only, and Slave-only releases. All I2C Controller IP Cores are available in Verilog RTL. For companies first pursuing FPGA emulation, Digital Blocks support services will fully assist..
To learn more about the I2C Controller Reference Designs & Evaluations, please contact Digital Blocks.
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