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| Digital Blocks is a member of the OCP International Partnership (OCP-IP), a non-profit semiconductor industry consortium formed to administer the support, promotion and enhancement of the Open Core Protocol (OCP) specification. OCP is the only fully supported, openly licensed, complete interface socket for intellectual property (IP) cores. OCP addresses design, verification and testing issues common to IP core reuse in "plug-and-play" system-on-chip (SOC) products. Digital Blocks actively develops its IP cores with a OCP specified interface socket. |
| Partners |
| Digital Blocks is a member of the Altera Megafunction Partners Program. Digital Blocks offers it IP cores in VHDL/Verilog and technology-specfic netlists formats targeting Altera devices, including all members of the Cyclone I / II and Stratix II / II GX / III series of FPGAs; MAX I / II series of CPLDs; and Hardcopy I / II series of structured ASICs. |
| Digital Blocks is a member of the Altera OpenCore Program. The OpenCore Program allows you to parameterize, compile, and simulate Digital Blocks IP cores within Altera's Quartus II design tools. Through the addtional OpenCore Plus Program you can generate a programming file and test Digital Blocks' IP core in hardware for a specified amount of time. To request an OpenCore evaluation, please visit out Evaluation Request page. |
| Copyright © Digital Blocks, Inc. 2005-2008. ALL RIGHTS RESERVED All other trademarks and service marks are the property of their respective owners. |
| Digital Blocks is a member of the SignOnce IP License Common License Consortium. The SignOnce IP License offers a common set of IP licenses that streamlines the licensing of IP cores by users. The SignOnce IP Consortium offers Project License and Site License agreements. To learn more, please visit the consortium at www.xilinx.com/ipcenter/signonce |
Digital Blocks
Semiconductor IP
Semiconductor IP