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| Welcome to Digital Blocks |
Digital Blocks' offers semiconductor Intellectual Property (IP) cores for embedded
processor and video system designers. We offer synthesizable RTL VHDL and
Verilog IP cores for System-on-Chip (SoC) ASSP, ASIC, and FPGA designers.
processor and video system designers. We offer synthesizable RTL VHDL and
Verilog IP cores for System-on-Chip (SoC) ASSP, ASIC, and FPGA designers.
Programmable Interrupt Controllers
Our Programmable Interrupt Controller series consists of the DB8259A (Static Design) and
DB8259S (Synchronous) interrupt controllers. Both are full-featured equivalents of the industry
standard Intel 8259A / Intersil 82C59A / NEC uPD8259 interrupt controllers. Available in VHDL
and Verilog, these 8259 IP cores come with a comprehensive test suite, synthesis scripts, data
sheet, and user manual.
DB8259S (Synchronous) interrupt controllers. Both are full-featured equivalents of the industry
standard Intel 8259A / Intersil 82C59A / NEC uPD8259 interrupt controllers. Available in VHDL
and Verilog, these 8259 IP cores come with a comprehensive test suite, synthesis scripts, data
sheet, and user manual.
Display Controllers
Our Display Controller series consists of the DB9000AHB, the DB9000OCP, and the DB9000AVLN
LCD Controllers and the DB6845 CRT Controller.
The DB9000AHB TFT LCD Controller interfaces frame buffer memory and an ARM processor via the
AMBA 2.0 AHB bus frabric to TFT LCD panels. Available in Verilog and VHDL, the silicon-verified
DB9000AHB IP core comes with a comprehensive test suite, synthesis scripts, data sheet, and user
manual.
The DB9000OCP TFT LCD Controller interfaces frame buffer memory and a variety of processors via
the Open Core Protocol Specification 2.2 interface to TFT LCD panels. Available in Verilog and
VHDL, the silicon-verified DB9000OCP IP core comes with a comprehensive test suite, synthesis
scripts, data sheet, and user manual.
The DB9000AVLN TFT LCD Controller interfaces frame buffer memory and an Altera NIOS II
processor via the Altera Avalon Bus to TFT LCD panels. Available in Verilog and VHDL, the
silicon-verified DB9000AVLN IP core comes with a comprehensive test suite, software driver, synthesis
scripts, data sheet, and user manual.
LCD Controllers and the DB6845 CRT Controller.
The DB9000AHB TFT LCD Controller interfaces frame buffer memory and an ARM processor via the
AMBA 2.0 AHB bus frabric to TFT LCD panels. Available in Verilog and VHDL, the silicon-verified
DB9000AHB IP core comes with a comprehensive test suite, synthesis scripts, data sheet, and user
manual.
The DB9000OCP TFT LCD Controller interfaces frame buffer memory and a variety of processors via
the Open Core Protocol Specification 2.2 interface to TFT LCD panels. Available in Verilog and
VHDL, the silicon-verified DB9000OCP IP core comes with a comprehensive test suite, synthesis
scripts, data sheet, and user manual.
The DB9000AVLN TFT LCD Controller interfaces frame buffer memory and an Altera NIOS II
processor via the Altera Avalon Bus to TFT LCD panels. Available in Verilog and VHDL, the
silicon-verified DB9000AVLN IP core comes with a comprehensive test suite, software driver, synthesis
scripts, data sheet, and user manual.
The DB6845 CRT Controller is a full-featured equivalent to the industry standard MC6845.
Available in VHDL, the DB6845 CRT Controller is a customer-proven IP core available with a
comprehensive test suite, synthesis scripts, data sheet, and user manual.
Available in VHDL, the DB6845 CRT Controller is a customer-proven IP core available with a
comprehensive test suite, synthesis scripts, data sheet, and user manual.
Video Signal Processing
Our Video Signal Processing IP Core consists of the DB1800 NTSC / PAL / SECAM Video
Sync Separator. The DB1800 accepts a composite video signal and outputs horizontal sync,
vertical sync, chroma burst blanking, and field 1 or 2 detection. Available in Verilog, this IP core
comes with a comprehensive test suite, synthesis scripts, data sheet, and user manual.
Sync Separator. The DB1800 accepts a composite video signal and outputs horizontal sync,
vertical sync, chroma burst blanking, and field 1 or 2 detection. Available in Verilog, this IP core
comes with a comprehensive test suite, synthesis scripts, data sheet, and user manual.
Programmable Keyboard / Display Interface
Programmable Peripheral Interface
Our Programmable Peripheral Interface IP Core consists of the DB8255A, providing 24 lines of
programmable I/O. The DB8255A is a full-featured equivalent to the industry standard Intel
8255A / 82C55A and Intersil 82C55A. Available in VHDL, this IP core comes with a
comprehensive test suite, synthesis scripts, data sheet, and user manual.
programmable I/O. The DB8255A is a full-featured equivalent to the industry standard Intel
8255A / 82C55A and Intersil 82C55A. Available in VHDL, this IP core comes with a
comprehensive test suite, synthesis scripts, data sheet, and user manual.
Digital Blocks
Semiconductor IP
Semiconductor IP
Our Programmable Keyboard / Display Interface IP Core consists of the DB8279, which
simultaneously and independently interfaces a keyboard and display to a microprocessor. The
DB8279 is equivalent to the industry standard Intel 8279. Available in VHDL, this IP core comes
with a comprehensive test suite, synthesis scripts, data sheet, and user manual.
simultaneously and independently interfaces a keyboard and display to a microprocessor. The
DB8279 is equivalent to the industry standard Intel 8279. Available in VHDL, this IP core comes
with a comprehensive test suite, synthesis scripts, data sheet, and user manual.
| Copyright © Digital Blocks, Inc. 2005-2008. ALL RIGHTS RESERVED |
| What's New |
| 18 July 2008 Digital Blocks Announces I2C-Master Controller IP Core for ARM AMBA 2.0 APB and Altera NIOS II Avalon Interconnects |
I2C - Inter-Integrated Circuit Controller
| The DB9000AVLN is SOPC Builder Ready and AMPP Approved by Altera Corporation. |
| The SOPC Builder Ready designation by Altera certifies the DB9000AVLN IP Core contains an Avalon compatible bus interface, SOPC Builder support files, push-button SOPC Builder flow, software support files, and that the DB9000AVLN is both software and hardware tested. |
| The AMPP Approved Certification designation by Altera certifies the DB9000AVLN IP Core compiles in the Altera standard design software flow, is optimized for the most current Altera device architectures, and includes good quality documentation. |
Digital Blocks' I2C Controller IP Cores consists of the DB-I2C-M-APB for the AMBA 2.0 APB
Bus and the DB-I2C-M-AVLN for the Avalon Bus. The I2C Controllers are offered with
parameterized FIFOs and Smart Control for processors with high performance algorithm
requirements, in a Master only function for a small VLSI footprint. Available in Verilog, this IP core
comes with a comprehensive test suite, synthesis scripts, data sheet, C software directing I2C Bus
tranactions, and a user manual.
Bus and the DB-I2C-M-AVLN for the Avalon Bus. The I2C Controllers are offered with
parameterized FIFOs and Smart Control for processors with high performance algorithm
requirements, in a Master only function for a small VLSI footprint. Available in Verilog, this IP core
comes with a comprehensive test suite, synthesis scripts, data sheet, C software directing I2C Bus
tranactions, and a user manual.