Digital Blocks offers full featured SPI Controller IP Verilog Cores, with releases containing Master/Slave, Master-only, and Slave-only functions, as well as a Quad/Dual/Single SPI Master Flash Memory Controller Verilog IP Core.

SPI Controller Verilog IP Cores

The Master/Slave SPI Controller IP Cores (Verilog Cores DB-SPI-MS-AMBA, DB-SPI-MS-AVLN) contain a parameterized FIFO, Control Unit, & Interrupt Controller to fully off-load the SPI transfer from the processor. The full off-load capabilities target applications with higher performance algorithm requirements or minimal software development plans.

The Master-only SPI Controller IP Cores (Verilog Cores DB-SPI-M-AMBA) have the Master function from the Master/Slave releases, with parameterized FIFO, SPI Master Control Unit, & Interrupt Controller, to fully off-load the SPI transfers from the processor. The Master-only SPI Controller IP offers a smaller VLSI footprint.

The Slave-only SPI Controller IP Cores (Verilog Cores DB-SPI-S-AMBA) have the Slave function from the Master/Slave releases, with parameterized FIFO, SPI Slave Control Unit, & Interrupt Controller, to fully off-load the SPI transfers from the processor. The Slave-only SPI Controller IP offers a smaller VLSI footprint.

The SPI Master Flash Memory Controller Verilog IP Core (Verilog Core DB-SPI-FLASH-MEM-AXI) supports Quad/Dual/Single Flash Memory, with a CPU AMBA Slave interface to the SPI Master function containing a parameterized FIFO, SPI Master Control Unit, & Interrupt Controller, and an AMBA AXI Slave Infterface, for Boot and Execute-In-Place (XIP) via the AXI Interconnect.

To learn more about the SPI Family of IP Cores Digital Blocks offers, including Master/Slave, Master-only and Slave-only IP Cores, as well as Interconnect fabrics for AMBA AXI & APB & AHB & Altera Avalon, please see the IP Cores page or contact Digital Blocks.

SPI Controller Reference Designs & Evaluations

Digital Blocks offers SPI Controller IP Core reference designs & evaluations that enable you to accelerate the design-in of an SPI Bus within your system.

For FPGA design teams, we offer AMBA Interfaces to CPUs in all Master/Slave, Master-only, and Slave-only releases. For Altera® FPGAs, we additionally offer the Avalon Interface to the Nios® II embedded processor. All SPI Controller IP Cores are available in Verilog RTL or, for lower costs, Altera® or Xilinx® netlist formats.

For ASIC, ASSP, Custom IC design teams, we offer AMBA Interfaces to CPUs in all Master/Slave, Master-only, and Slave-only releases. All SPI Controller IP Cores are available in Verilog RTL. For companies first pursuing FPGA emulation, Digital Blocks support services will fully assist..

To learn more about the SPI Controller Reference Designs & Evaluations, please contact Digital Blocks.