The TFT LCD Controller Reference Design from Digital Blocks enables hardware designers to accelerate the design-in of TFT LCD panel displays into their system. The Reference Design centers on Digital Blocks DB9000AVLN TFT LCD Controller IP Core, which is available in Altera® netlist or Verilog RTL formats.

The DB9000AVLN contains an Altera Avalon® System Interconnect for interface to the NIOS® II processor and SDRAM or SRAM controllers. Either memory can serve as the Frame Buffer. Software supplied with the Reference Design runs on the NIOS®II processor to place an image in Frame Buffer memory and setup & invoke the DB9000AVLN to drive the LCD panel.

Utilizing Altera’s Quartus II tools, the Reference Design places into an Altera Cyclone, Stratix, or Arria series FPGA development kit. All Altera FPGAs are supported.

In addition to supporting the Altera Avalon System Interconnect, the DB9000 Family of TFT LCD Controllers IP Cores & Reference Designs can connect via Qsys. Likewise, the DB9000 family member with AXI interconnect — the DB9000AXI — can connect via the AMBA AXI.interconnect fabric to a ARM® Cortex™-A9 processor within the Cyclone V and Arria® V SoC FPGAs.

The user can connect their LCD panel to the development kit with the fabrication of an appropriate cable.

To learn more about the TFT LCD Controller Reference Design, please contact Digital Blocks.