For Immediate Release
Digital Blocks Marks 20 Years of the DB9000 Display Controller IP Family
Field-proven TFT LCD / OLED controller IP, first released in 2006, now spans AXI5/AXI4 through
Avalon interconnects with independently licensable multi-window compositing, multi-lane UHD
output, image scaling, and display-integrity diagnostics
GLEN ROCK, New Jersey — July 28, 2026 —
Digital Blocks, Inc. today highlighted the continued expansion of its DB9000 family of
programmable Display Controller SystemVerilog IP Cores, first delivered to customers in 2006. Over
two decades of silicon-proven deployment, the DB9000 has grown from a compact baseline display
controller into a configurable display processing subsystem spanning 320×240 industrial
panels to 8K multi-lane UHD displays.
The family targets ASIC and FPGA design teams in medical / patient monitoring and imaging
consoles, industrial/HMI, aerospace and defense / avionics cockpit displays, automotive
instrument clusters and head-up displays, computer, monitor, consumer, AR/VR headset, IoT,
wearable, signage, gaming, broadcasting, point-of-sale and kiosk terminals, handheld/portable
instruments and test instrumentation applications.
Configure Once, Synthesize Only What You License
Every DB9000 shipment is synthesizable SystemVerilog RTL. Bus protocol, bus
width, memory technology, and FIFO sizing are set by `define and parameter before
synthesis, and each advanced feature is built into the gate count only when licensed and
enabled — an unlicensed feature costs zero silicon.
Baseline synthesis parameters include AMBA AXI5, AXI4, AXI3, AHB, AHB-Lite, AHB5, APB, or Altera
Avalon-MM bus selection; 32- to 512-bit master bus width; palette, FIFO, and cursor memories
pre-built for Xilinx, Altera, Actel, or generic vendor RAM; synchronous or asynchronous FIFOs
with configurable depth; and DFT test bus passthrough for scan and BIST insertion. Unused
Control & Status Register bits can be hardwired as parameters, typically halving VLSI
footprint versus a fully populated register set.
Advanced Options
Multi-window compositing
1, 2, 4, 8, or 16 independently positioned, DMA-fed overlay windows over the base screen,
with per-pixel alpha blending at 16/18/24 bpp, a 32×32 or 64×64 hardware cursor
requiring no host involvement per frame, and an in-line image scalar applied per plane.
Color space and chroma processing
YCbCr 4:2:2 and 4:2:0 up-sampling to 4:4:4, plus a programmable 4×4 conversion matrix
instantiable for the base screen and two overlay windows. A high dynamic range pixel path
is offered as a separate option.
Advanced panel interfaces
An OpenLDI V0.95 LVDS serializer, and a multi-port interface driving 1-, 2-, 4-, or 8-lane
output to DisplayPort, HDMI, V-by-One, MIPI, or LVDS panels with screen-area partitioning
for UHD and 8K. Dual display support drives independent left and right panels from one
pixel pipeline.
Dynamic content and diagnostics
A frame descriptor engine that reprograms frame buffer addresses every frame with no host
CPU intervention, on-demand test pattern generation, per-region CRC-802.3 checking with
retransmission or interrupt on error, and a frozen display monitor with optional automatic
self-reset.
Availability
The DB9000 Display Controller & Processor IP Core family is available now in synthesizable
Verilog. Deliverables include a comprehensive simulation test suite, technical datasheet, and
user manual. For product evaluation or pricing inquiries, please visit the
DB9000 Product Page.
About Digital Blocks, Inc.
Digital Blocks, Inc. develops and licenses semiconductor IP cores for ASIC and FPGA designs,
including Display Controllers, 2D Graphics Engines, DMA Controllers, RTP & UDP Hardware
Stacks, and AMBA Peripherals eSPI/I3C/I2C/xSPI bus interface cores, delivered as synthesizable
RTL with verification suites, software drivers, synthesis scripts, and documentation.
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