AHB5 DMA Controller IP Core
Multi-channel scatter-gather DMA for AMBA® 5 AHB systems.
SystemVerilog RTL, 1 to 126 channels, 8- to 1024-bit data paths.
Channel count and data width are set at build time. A dedicated AHB5 read manager fetches descriptors and source data while a dedicated AHB5 write manager writes the destination, so reads and writes run at the same time. Any source and destination byte alignment, any length, with no burst crossing a 1 KB boundary.
Bus use: 128-bit data path, cycle-accurate RTL simulation, zero wait states. Coverage after reviewed waivers.
At a glance
Synthesizable SystemVerilog RTL with a self-checking test bench, drivers and a C++ cycle model.
| Bus protocol | AMBA 5 AHB (IHI 0033B) |
|---|---|
| DMA channels | 1 to 126, build-time option |
| DMA data width | 8, 16, 32, 64, 128, 256, 512 or 1024 bits |
| Addressing | 32-bit (HADDR[31:0]) |
| Manager ports | 2: read (descriptors and source data), write (destination data) |
| Register port | AHB5 subordinate, 32-bit, 4 KB window, zero wait states |
| Bursts | INCR4, INCR8, INCR16 or a programmed 1 to 256 beats, issued as bursts of up to 16 beats; clipped at 1 KB |
| Descriptors | 16-byte nodes; up to 32 prefetched per channel; 1 byte to 16 MB per node |
|---|---|
| Data buffer | 32 words of the data width per channel, with a byte rotator |
| Alignment | Any source and destination byte, any length |
| Hardware pacing | DREQ / DACK per channel, for reads and for writes (programmable option per channel) |
| Security | TrustZone: HNONSEC and HPROT per channel, register lock |
| Interrupts | Per-channel outputs plus one processor aggregate interrupt |
| Clocking | Single clock (hclk), fully synchronous |
Measured throughput
Cycle-accurate RTL simulation of a 128-bit build (16 bytes per cycle peak on each manager) against AHB5 memory models with full-rate HREADY and programmable wait states, counted from the first descriptor fetch to the last accepted write beat.
| Scenario | B / cycle | Bus use |
|---|---|---|
| Two channels, 64 KB each, INCR16 | 14.18 | 88.6 % |
| Sixteen channels, 8 KB each, INCR16 | 14.12 | 88.3 % |
| One channel, 64 KB, INCR16 | 12.73 | 79.6 % |
| One channel, 64 KB, INCR4 | 7.99 | 49.9 % |
| One channel, unaligned source and destination | 11.53 | 72.1 % |
| One channel, 1 wait state on every beat | 7.08 | 44.2 % |
| 16 × 1 KB descriptor chain | 9.88 | 61.8 % |
| Descriptor node boundary | 23 cycles | |
The 32-bit default build reaches the same bus use (two channels: 3.55 of 4 bytes per cycle, 88.8 %). Throughput scales with the data width; results depend on the interconnect, memory and configuration.
Architecture
Each channel has its own registers, descriptor processor with a 32-node prefetch queue, read and write engines and a 32-word data FIFO with a byte rotator. Two shared AHB5 managers serve all channels by round robin: the read manager carries descriptor fetches and source reads, the write manager the destination writes, including the narrow head and tail transfers of unaligned blocks.
System Architecture Example
Below is an example System View of the AHB5 DMA Controller IP.
Features
Scatter-gather
16-byte descriptor nodes with 32-bit source, destination and next address and a 24-bit length (1 byte to 16 MB per node). Chained and ring lists, list start or branch, re-start and wait-on-restart; up to 32 nodes prefetched per channel.
Transfer types
Memory to memory, memory to peripheral, peripheral to memory and peripheral to peripheral. Fixed-address (FIFO) reads and writes; per-channel DREQ / DACK pacing of read and write bursts.
Unaligned transfers
Any source and destination byte offset, any length. Whole-word reads through a byte rotator; the write manager issues naturally aligned narrow transfers for the head and tail of the block.
AHB5 bursts
INCR4, INCR8 or INCR16 per channel, or a programmed length; every burst stops at a 1 KB boundary and at the end of the block. Any number of wait states; ERROR responses are captured per channel.
Security
TrustZone attributes per channel: HNONSEC and HPROT for each manager, and a lock that hides a channel’s registers from Non-secure accesses.
Status and interrupts
Per-channel status, masks and interrupt outputs; global status, mask and vector registers (one bank per 32 channels) and one processor interrupt. Write-1-to-clear never loses a same-cycle hardware event.
Integrity
Optional per-byte parity checking on data and descriptor reads; parity generated on writes.
Implementation
Single clock, fully synchronous, with no gated clocks and no internal tri-states. Technology-independent RTL for ASIC and FPGA. A self-describing identification register reports channel count, data width and revision.
Verification
Delivered with the self-checking test bench used for sign-off. Every transferred byte is checked, and the channel- and width-generic tests run over every configured channel.
Builds verified at sign-off
Plus a 126-channel, 1024-bit corner build: 14 builds in all, every test passing.
Sign-off build checks
- AHB5 protocol assertions on both managers and the register port, in every test
- A descriptor-length monitor in every test: each descriptor writes exactly its length
- Memory models with wait states, ERROR responses and parity error injection
- 35 of 35 tests passing; 100 % branch, statement and FSM coverage after reviewed waivers
Deliverables
- Synthesizable SystemVerilog RTL (IEEE 1800-2012) with a flat-pin top level; FPGA netlists on request
- Synopsys Design Constraints, compile-ordered filelist, lint script and waivers
- Self-checking test bench: AHB5 memory models, protocol assertions and a regression driver with coverage scripts
- C++ cycle model
- Bare-metal C driver with reference program; Linux platform driver, UAPI header and device-tree example
- Data sheet, Technical Reference Manual, IP Integration Guide, IP-XACT descriptor, coverage report and test matrix
Learn more about the AHB5 DMA Controller
Contact Digital Blocks for technical details, pricing and evaluation options.
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