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DB9000AXI Display Controller

Digital Blocks DB9000AXI4 Display Controller interfaces Frame Buffer Memory via the AMBA AXI Protocol fabric to a Display Panel with programmable resolutions from 320×240 (QVGA) up through 1920×1080 HD, 4K, and 8K.

Releases supporting baseline display requirements and advanced releases with following optional display processing features:

• Overlay Windows
• Hardware Cursor
• High Dynamic Range (HDR)

Overlay Windows option comes with advanced composition features:

• Alpha Blending
• Color Space Conversion (CSC)
• 4:2:2 YCrCb with Re-sampling & CSC to RGB
• Programmable size, placement, & format

The DB9000 Display Controller & Processor family of IP Cores is an ASIC/FPGA design team’s most versatile choice.

AXI4 DMA Controller

The Digital Blocks DB-DMAC-MC-AXI4 Verilog RTL IP Core is a Multi-Channel DMA Controller supporting 1 – 16 independent data transfers. The DB-DMAC-MC-AXI excels at high data throughput on both small and large data sets. Standard IP releases of the number of DMA Controller Channels are 1, 2, 4, 8, 16 with development plans to expand from 32 to 256.

Releases support key features:

• Each DMA Channel has independent DMA Read and Write Controllers with top-level overhead control and parameterized FIFO
• Transfers to any combination of source or destination Memory and Peripherals
• Support for unique peripherals with sideband flow control signals
• Scatter-Gather linked-list control of data transfers with interrupt reporting
• User programmed AXI3 bursts of 1,4,8,16 beats and AXI4 bursts of 1-256 beats and full support for 4K boundary crossing
• AXI Data Width options: 8 / 16 / 32 / 64 / 128 / 256 / 512 / 1024
• Users can add verified advanced DMA features, choosing according to requirements to minimize silicon area and licensing costs
• Specification and test bench with test cases

The DMA Controller family of IP Cores contains release configurations with AXI4-Stream Interfaces for transfers between a streaming data interface and a memory-mapped interface.

eSPI Master/Slave Controller

The DB-eSPI-SPI-MS-APB Controller IP conforms to the Enhanced Serial Peripheral Interface (eSPI) Specification, satisfying the eSPI Bus Protocol and Transaction and Link Layer requirements. The DB-eSPI-SPI-MS-APB can be programmed to function as an eSPI Master or eSPI Slave, or a SPI Master or SPI Slave. Additional AMBA Interconnects supported are AXI or AHB.

SPI Master/Slave Controller

The DB-SPI-MS-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS contains an AMBA AXI, AHB, or APB Bus Interface for interfacing a microprocessor to external SPI Master/Slave devices.

SPI Master/Slave XIP Controller

The DB-SPI-XIP-FLASH-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting access to Single/Dual/Quad/Octal SPI Flash Memory devices by way of Processor Execute-in-Place (XIP).

I3C Master/Slave Controller

The Digital Blocks DB-I3C-BASIC-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – BASIC v1.0 Improved Inter Integrated Circuit specification. The I3C Basic serves as an upgrade path to the I2C standard.

I2C Master/Slave Controller

The Digital Blocks DB-I2C-MS-Hs-Mode Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus to an I2C Bus in Hs-Mode (3.4 Mbit/s) / Fast-Mode Plus (1 Mbit/s) / Fast-Mode (400 Kbit/s) / Standard-Mode (100 Kbit/s).