Digital Blocks is a member of the ARM Connected Community, supporting the ARM architecture with our innovative TFT LCD Controller, 2D Graphics, Networking, and Peripheral IP Cores for Silicon SoC design teams.
Digital Blocks membership in MIPI has resulted in MIPI standard I3C for sensors and DSI-2 for Display Interface, with unique system-level integration features.
Digital Blocks is a member of the Altera Megafunction Partners Program. Digital Blocks offers it IP cores in VHDL/Verilog and technology-specific netlists formats targeting Altera devices, including all members of the Cyclone, Arria, & Stratix series of FPGAs; MAX series of CPLDs; and Hardcopy series of structured ASICs. Digital Blocks offers its AXI interconnect IP Cores targeting Altera SoC FPGAs.
Digital Blocks is a member of the Altera OpenCore Program. The OpenCore Program allows you to parameterize, compile, and simulate Digital Blocks IP cores within Altera’s Quartus II design tools. Through the additional OpenCore Plus Program you can generate a programming file and test Digital Blocks’ IP core in hardware for a specified amount of time. To request an OpenCore evaluation, please visit out Evaluation Request page.
Digital Blocks is an approved Microsemi CompanionCore Partner offering optimized IP cores for Microsemi FPGAs and SoC FPGAs. Digital Blocks offers its AXI, AHB, APB interconnect IP Cores targeting Microsemi FPGAs.
Digital Blocks is a member of the Society for Information Displays. SID brings together professionals in all of the technical and business disciplines that relate to Display Technologies, and enables Digital Blocks to maintain Display leadership for its customers.
Digital Blocks is a member of the OCP International Partnership (OCP-IP), a non-profit semiconductor industry consortium formed to administer the support, promotion and enhancement of the Open Core Protocol (OCP) specification. OCP is the only fully supported, openly licensed, complete interface socket for intellectual property (IP) cores. OCP addresses design, verification and testing issues common to IP core reuse in “plug-and-play” system-on-chip (SOC) products. Digital Blocks actively develops its IP cores with a OCP specified interface socket.
Digital Blocks is a member of the The SPIRIT Consortium, which provides a unified set of specifications based on IP meta-data, the IP-XACT specifications, for importing complex IP bundles into System-on-Chip (SoC) design tool sets, and exchanging design descriptions between tools.
Digital Blocks is a member of the SignOnce IP License Common License Consortium. The SignOnce IP License offers a common set of IP licenses that streamlines the licensing of IP cores by users. The SignOnce IP Consortium offers Project License and Site License agreements. To learn more, please visit the consortium at https://www.xilinx.com/alliance/signonce.html.
Digital Blocks is a member of the D & R Partner Program. Through the D & R Partner Program, Digital Blocks provides global companies with updated information on Digital Blocks IP Core & Design Services offerings.
Digital Blocks is a ChipEstimate IP Partner. Through the IP Partner Program, Digital Blocks provides global companies with updated information on Digital Blocks IP Core offerings.
Digital Blocks is a member of the AnySilicon Program. Through AnySilicon, Digital Blocks provides global ASIC design teams updated information on Digital Blocks IP Core & Design Services offerings.
Digital Blocks is a member of Accellera. Through Accellera, Digital Blocks stays up-to-date with the latest design and verification standards that impact the global System-on-Chip (SoC) development industry.