Overview
Digital Blocks’ RTP/UDP/IP Verilog IP Cores implement RTP, UDP, IP, and ARP
entirely in hardware, with optional DHCP, ICMP, IGMP, and VLAN support —
removing network protocol processing from the host CPU.
- Full Protocol Stack in Hardware: RTP, UDP, IP, and ARP processing at wire speed, with optional DHCP, ICMP, IGMP, and VLAN support.
- Scalable Engine Count: Configurable from 1 to N parallel RTP/UDP/IP processing engines per release, sized to the target video-streaming performance.
- Unicast & Multicast UDP: Line-rate Unicast and Multicast video streaming, plus general-purpose low-latency data transport offload from the host processor.
- FPGA/ASIC & MAC Agnostic: Synthesizable RTL that targets AMD/Xilinx, Intel/Altera, and third-party Ethernet MAC devices.
RTP/UDP/IP Video Network Streaming
Two hardware-accelerated cores put real-time video directly on the wire, removing
RTP/UDP/IP protocol processing entirely from the host CPU: one for uncompressed
RGB/YUV video streams, one for compressed H.264 NAL streams.
DB-RTP-UDP-IP-NAL
H.264/H.265 NAL Video Streams Packet Processing
- Large-NALU Fragmentation: Hardware RFC 6184 FU-A engine automatically splits any oversized H.264 NAL unit into an MTU-sized packet burst — no jumbo frames, no host software.
- Full Protocol Stack in Hardware: RTP, UDP, IP, and ARP processing, checksums, and framing at wire speed with zero host CPU load.
- Multi-Stream Concurrent TX/RX: Multiple simultaneous video streams to and from low-latency hardware video codecs.
- Software-Optional Operation: Runs from hardwired register tie-offs with no external processor or driver, or under full AXI4-Lite/Avalon-MM control.
DB-RTP-UDP-IP-AV
Uncompressed RGB/YUV Video Streams
- RFC 4175 Payload Framing: Hardware packetization of raw RGB/YUV video into standards-compliant RTP payloads for uncompressed video-over-IP.
- Configurable Line Packing: 1, 2, or 4 RTP packets per video line, tunable to the resolution and network profile.
- Independent RX/TX Datapaths: Separate receive and transmit top-level cores, each with its own AXI4-Lite register interface.
- Multicast, Multi-Stream I/O: Simultaneous delivery across up to 12 concurrent I/O streams.
UDP/IP Hard Protocol Stack
The DB-UDP-IP family is a UDP/IP off-load engine for SoC FPGA/ASIC designs,
delivered as independent Transmit and Receive hardware blocks with
configurable port counts and an optional integrated DMA Controller. Six
pin-compatible variants scale from 1 GbE to 100 GbE Ethernet MAC speeds.
- Independent TX/RX Blocks: Separate transmit and receive top-level cores — transmit-only or receive-only configurations save logic.
- 1–32 Configurable Ports: Each port carries its own register set; receive ports use a 6-tuple session-matching CAM (MAC/IP/UDP fields) for filtering and multicast fan-out.
- Hardware Checksums, ARP & ICMP: In-line IP/UDP checksum generation and validation, ARP client/server with timeout cache, and autonomous ICMP echo (ping) response.
- Flexible Register & DMA Access: 32-bit AXI4-Lite, APB, or AHB (Avalon-MM) control with interrupts, plus an optional integrated DMA Controller for direct memory-to-network transfer.
Each link opens the variant’s PDF datasheet.