eSPI Controller/Target &
SPI Memory Controller SystemVerilog IP Cores

Digital Blocks Full-Featured eSPI Controller/Target & SPI Memory Controller & Standard, General Purpose SPI Master/Slave IP SystemVerilog Cores

Digital Blocks offers silicon-proven, full-featured eSPI Controller/Target SystemVerilog RTL IP cores, available in Controller/Target, Controller-only, and Target-only configurations. The IP is compliant with the Intel^® Enhanced Serial Peripheral Interface (eSPI): Interface Base Specification for Client and Server Platforms, Revision 1.6 (March 2025), and is optimized for SoC, ASIC, and FPGA designs.

Digital Blocks also offers silicon-proven SPI Flash Memory Controller and SPI MRAM/PSRAM Controller SystemVerilog IP cores, enabling high-performance CPU access to serial memory devices with optional Execute-In-Place (XIP) support for embedded SoC, ASIC, and FPGA applications.

In addition, Digital Blocks provides robust, feature-rich legacy SPI Controller SystemVerilog IP cores supporting Master/Slave, Master-only, and Slave-only configurations for a wide range of SPI peripheral interfaces.

eSPI Controller/Target RTL SystemVerilog IP Core

The DB-eSPI-SPI-Controller-Target-AMBA Controller/Target IP conforms to the Enhanced Serial Peripheral Interface (eSPI) Specification, satisfying the eSPI Bus Protocol and Transaction and Link Layer requirements. The DB-eSPI-SPI-Controller-Target-AMBA can be programmed to function as an eSPI Controller (aka Master) or eSPI Target (aka Slave), or a SPI Master or SPI Slave. AMBA Interconnects supported are AXI or AHB or APB.

The Digital Blocks eSPI Controller/Target IP Core is architected for modern SoC, EC, and BMC platforms requiring Intel®-style or AMD®-style eSPI connectivity between host processors, embedded controllers, management controllers, peripherals, and platform subsystems. Additionally, the core enables high-performance, low-pin-count system integration and provides a standards-compliant migration path from legacy LPC interfaces. Overview Features are as follows:

• Integrated eSPI 1.6 Controller + Target: single SystemVerilog IP core implementing both the Controller (Master) and Target (Slave) functions of the Intel Enhanced Serial Peripheral Interface (eSPI) Base Specification Rev. 1.6 (Intel document 841685); role selected at integration/run time. Interoperable with eSPI 1.5 link partners.
• All four eSPI channels: Ch 0 Peripheral (Posted and Non-Posted), Ch 1 Virtual Wire (up to 64 groups), Ch 2 Out-of-Band / tunneled SMBus messages, Ch 3 Flash Access in both CAFS and TAFS modes (including RPMC OP1/OP2).
• Complete command set, both directions: short I/O and short Memory cycles (1/2/4-byte), PUT_NP / GET_NP and PUT_PC / GET_PC with all Peripheral cycle types, Virtual Wire, OOB, all four Flash commands, GET_STATUS, SET_CONFIGURATION / GET_CONFIGURATION, and In-Band RESET.
• Operating modes: Single (x1), Dual (x2), and Quad (x4) I/O lanes; programmable maximum payload size of 64 / 128 / 256 bytes; per-frame CRC-8 generation and checking.
• Controller-role features:
  • Drives up to 8 eSPI Targets with per-Target chip selects; ALERT# monitoring plus in-band I/O[1] alert detection
  • Phase-aware wait-state (0x0F) filtering and in-flight response Length-field decode (LDE)
  • Response-code decoding with host interrupt on FATAL_ERROR / NON_FATAL_ERROR / DEFER; ALERT#-driven retrieval of deferred completions
  • IPMI 2.0 KCS and BT transactions over eSPI short I/O cycles; optional zero-software autonomous Host-I/O-to-eSPI bridge (auto-I/O)
• Target-role features:
  • Full reactive response engine: ACCEPT (with optional channel-specific modifier), DEFER, WAIT_STATE, NON_FATAL_ERROR, FATAL_ERROR, NO_RESPONSE
  • Hardware protocol enforcement: FATAL_ERROR on GET-without-AVAIL / PUT-without-FREE; NO_RESPONSE on command-phase CRC error, invalid opcode, or unsupported cycle type
  • Live eSPI Status Word (real-time per-channel FREE / AVAIL); programmable wait-state insertion with DEFER on timeout; C1C0-authoritative short-cycle completions
  • ALERT# generation, In-Band Reset detection, and RESET#-qualified recovery with no bus re-initialization required
• System interface: AMBA APB or AXI4-Lite slave for registers and FIFOs; per-channel parameterizable dual-clock TX/RX FIFOs with programmable thresholds; two-level interrupt controller with per-source mask, status, and vector registers; optional DMA controller.
• Legacy SPI fall-back: standard SPI Master and SPI Slave modes (Modes 0–3, Half/Full-Duplex, programmable frame formats, LSB/MSB-first).
• Verification & deliverables: UVM environment plus self-checking directed regression (dual-instance Controller ↔ Target testbench on a shared bus), code and functional coverage reports, synthesizable SystemVerilog RTL with SDC constraints, bare-metal C and Linux drivers, Technical Reference Manual and Integration Guide.

The architecture provides complete processor offload for eSPI transactions and enables deterministic host-to-peripheral communication in server, embedded controller, networking, and industrial SoC platforms. The core integrates cleanly into AMBA-based system fabrics and supports scalable performance configurations.

eSPI Controller RTL SystemVerilog IP Core

The DB-eSPI-Controller-AMBA Controller IP conforms to the Enhanced Serial Peripheral Interface (eSPI) Specification, satisfying the eSPI Bus Protocol and Transaction and Link Layer Master requirements. The DB-eSPI-Controller-AMBA functions as an eSPI Controller (aka Master) or a SPI Master. AMBA Interconnects supported are AXI or AHB or APB.

The Digital Blocks eSPI Controller IP Core is architected for modern SoC and host platforms requiring Intel®-style or AMD®-style eSPI connectivity to downstream embedded controllers (EC), baseboard management controllers (BMC), flash memory, and peripheral subsystems. Additionally, the core enables high-performance, low-pin-count system integration and provides a standards-compliant migration path from legacy LPC host interfaces. Overview Features are as follows:

• eSPI 1.6 Controller (Master): full compliance to the Intel Enhanced Serial Peripheral Interface (eSPI) Base Specification Rev. 1.6 (Intel document 841685), Controller function, in synthesizable SystemVerilog RTL; interoperable with eSPI 1.5 Targets.
• All four eSPI channels: Ch 0 Peripheral (Posted and Non-Posted), Ch 1 Virtual Wire (up to 64 groups), Ch 2 Out-of-Band / tunneled SMBus messages, Ch 3 Flash Access in both CAFS and TAFS modes (including RPMC OP1/OP2).
• Complete command set: short I/O and short Memory cycles (1/2/4-byte), PUT_NP / GET_NP and PUT_PC / GET_PC with all Peripheral cycle types, Virtual Wire, OOB, all four Flash commands, GET_STATUS, SET_CONFIGURATION / GET_CONFIGURATION, and In-Band RESET.
• Operating modes: Single (x1), Dual (x2), and Quad (x4) I/O lanes; programmable maximum payload size of 64 / 128 / 256 bytes; per-frame CRC-8 generation and checking; full command/response framing off-loaded from the host CPU.
• Controller features:
  • Drives up to 8 eSPI Targets with per-Target chip selects; ALERT# monitoring plus in-band I/O[1] alert detection
  • Phase-aware wait-state (0x0F) filtering and in-flight response Length-field decode (LDE)
  • Response-code decoding with host interrupt on FATAL_ERROR / NON_FATAL_ERROR / DEFER; ALERT#-driven retrieval of deferred completions
  • Software-initiated In-Band Reset generation to external Targets
  • In software, IPMI 2.0 KCS and BT transactions over eSPI short I/O cycles; optional zero-software RTL autonomous Host-I/O-to-eSPI bridge (auto-I/O)
• System interface: AMBA APB / AHB / AXI4-Lite slave for registers and FIFOs; independent dual-clock TX/RX FIFOs (default 256 B, parameterizable 4 – 4096 B) with programmable thresholds; programmable SCK divider or external SCK source; combined interrupt output with per-source mask, status, and vector registers; optional DMA controller.
• Legacy SPI fall-back: standard SPI Master mode (Modes 0–3, Half/Full-Duplex, up to 8 Slave Selects, programmable frame formats, LSB/MSB-first).
• Verification & deliverables: self-checking regression suite covering all channels, lane widths, and error scenarios with code and functional coverage reports; SDC constraints, clean lint/CDC, scan-ready; bare-metal C and Linux drivers, Technical Reference Manual and Integration Guide.

The architecture provides complete processor offload for eSPI master transactions and enables deterministic host-to-peripheral communication in server, desktop, networking, and industrial SoC platforms. The core integrates cleanly into AMBA-based system fabrics and supports scalable performance configurations.

eSPI Target RTL SystemVerilog IP Core

The DB-eSPI-Target-AMBA Target IP conforms to the Enhanced Serial Peripheral Interface (eSPI) Specification, satisfying the eSPI Bus Protocol and Transaction and Link Layer Target requirements. The DB-eSPI-Target-AMBA functions as an eSPI Target (aka Slave) or a SPI Slave. AMBA Interconnects supported are AXI or AHB or APB.

The Digital Blocks eSPI Target IP Core is architected for modern Embedded Controllers (EC), Baseboard Management Controllers (BMC), and peripheral platforms requiring Intel®-style or AMD®-style eSPI connectivity to an upstream host processor or chipset controller. Additionally, the core enables high-performance, low-pin-count system integration and provides a standards-compliant migration path for legacy LPC client interfaces. Overview Features are as follows:

• eSPI 1.6 Target (Slave): full compliance to the Intel Enhanced Serial Peripheral Interface (eSPI) Base Specification Rev. 1.6 (Intel document 841685), Target function, in synthesizable SystemVerilog RTL; interoperable with eSPI 1.5 Controllers.
• All four eSPI channels: Ch 0 Peripheral (Posted and Non-Posted), Ch 1 Virtual Wire (up to 64 groups), Ch 2 Out-of-Band / tunneled SMBus messages, Ch 3 Flash Access in both CAFS and TAFS modes — including TAFS PUT_FLASH_NP connected reads (immediate ACCEPT + data, or DEFER with GET_FLASH_C retrieval)
• Full reactive response engine: ACCEPT (with optional channel-specific modifier), DEFER, WAIT_STATE, NON_FATAL_ERROR, FATAL_ERROR, and NO_RESPONSE, generated per the specification.
• Operating modes: Single (x1), Dual (x2), and Quad (x4) I/O lanes accepted from the Controller’s SET_CONFIGURATION; maximum payload size of 64 / 128 / 256 bytes advertised in the GCC / CHxCC capability registers; per-frame CRC-8 generation and checking.
• Target features:
  • Hardware protocol enforcement: FATAL_ERROR on GET-without-AVAIL / PUT-without-FREE (channel FIFOs preserved); NO_RESPONSE on command-phase CRC error, invalid opcode, or unsupported cycle type; maximum-payload and maximum-read-request-size enforcement with read-boundary checking
  • Live eSPI Status Word: real-time per-channel FREE / AVAIL, gated by a CPU program word
  • Programmable wait-state insertion with early ACCEPT exit and DEFER on timeout; C1C0-authoritative short-cycle completions (1/2/4-byte)
  • ALERT# generation to the Controller (open-drain or push-pull), asserted on local interrupt events
  • In-Band Reset detection (restores lified recovery with no bus re-initialization required; sub-clock-width RESET# pulses reliably captured; unexpected CS# deassertion detected with clean tr
• System interface: AMBA APB or AXI4-Lite slave for registers and FIFOs (identical register map; AXI4-Lite variant validated for Ael parameterizable dual-clock TX/RX FIFOs sized for one worst-case packet at maximum payload (512 B data channels), with per-FIFO software flush; two-level interrupt coer-2 protocol-error/event bank ISR2 / IMR2 / IVR2); optional DMA controller.
• Legacy SPI fall-back:des 0–3, Half/Full-Duplex, programmable frame formats, LSB/MSB-first).
• Verification & deliverables: UVM environment (eSPI VIP, register model, directed + constrained-random tests) plus self-checking directed regression with an eSPI bus monitor, including negative protocol-enforcement testing; code and functional coverage reports; SDC constraints, clean lint/CDC, scan-ready; bare-metal C and Linux drivers, Technical Reference Manual and Integration Guide.

The architecture provides clean hardware-level responses to eSPI transactions, minimizing local processor overhead and ensuring precise timing compliance in server management, client computing, and embedded SoC subsystems. The core integrates cleanly into AMBA-based system fabrics and supports scalable performance configurations.

SPI Flash Memory Controller Verilog IP Core, with Optional XIP Feature

The SPI Flash Memory Controller SystemVerilog RTL IP Core (DB-SPI-XIP-FLASH-AMBA) provides high-performance access to Octal, Quad, Dual, and Single SPI Flash memory devices. Two configurations are available: a CPU Access version with a single AMBA Slave interface for processor-controlled Flash memory transactions, and a CPU + Execute-In-Place (XIP) version that adds a second dedicated AMBA Slave interface, allowing software to execute directly from external SPI Flash memory while maintaining independent CPU access. Both configurations integrate a high-performance SPI Master controller with parameterizable FIFOs and interrupt support.

SPI MRAM/PSRAM Memory Controller SystemVerilog IP Core, with Optional XIP Feature

The SPI MRAM/PSRAM Memory Controller SystemVerilog RTL IP Core (DB-SPI-M-PSRAM-AXI4) provides high-performance access to Octal, Quad, Dual, and Single SPI MRAM and Persistent SRAM (P-SRAM) devices. Octal operation is supported using dual-quad memory devices operating in x8 lock-step mode for maximum memory bandwidth. Two configurations are available: a CPU Access version with a single AMBA AXI4-Lite Slave interface for processor-controlled memory transactions, and a CPU + Memory-Mapped/XIP version that adds a second full AMBA AXI4 Slave interface, enabling software execution directly from external persistent memory while providing high-performance memory-mapped read and write access. Both configurations integrate a high-performance SPI Master controller with parameterizable FIFOs, interrupt support, and autonomous initialization and polling engines.

SPI Controller Verilog IP Cores

The Master/Slave SPI Controller IP Cores (Verilog Core DB-SPI-MS-AMBA, DB-SPI-MS-AVLN) contain a parameterized FIFO, Control Unit, & Interrupt Controller to fully off-load the SPI transfer from the processor. The full off-load capabilities target applications with higher performance algorithm requirements or minimal software development plans.

The Master-only SPI Controller IP Cores (Verilog Core DB-SPI-M-AMBA) have the Master function from the Master/Slave releases, with parameterized FIFO, SPI Master Control Unit, & Interrupt Controller, to fully off-load the SPI transfers from the processor. The Master-only SPI Controller IP offers a smaller VLSI footprint.

The Slave-only SPI Controller IP Cores (Verilog Core DB-SPI-S-AMBA) have the Slave function from the Master/Slave releases, with parameterized FIFO, SPI Slave Control Unit, & Interrupt Controller, to fully off-load the SPI transfers from the processor. The Slave-only SPI Controller IP offers a smaller VLSI footprint.

The SPI Slave AMBA Bridge (Verilog Core DB-SPI-S-AMBA) supports Slave SPI Bus transfers to/from an AMBA APB, AXI, or AHB Interconnect (also known as SPI2APB, SPI2AXI, SPI2AHB). The SPI Slave Controller receives SPI transactions with regard to an external SPI Master, and completes data transfers by mastering the APB, AXI, or AHB AMBA Interconnect, and typically completes the transfer with respect to user registers or memory. No CPU host is required.