Digital Blocks full featured SPI Controller IP Verilog Cores
Digital Blocks full featured SPI Controller IP Verilog Cores with releases containing Master/Slave, Master- and Slave-only functions, and SPI Flash Memory Controller Verilog IP Cores. SPI Flash Memory Controllers access SPI Flash by CPU with options for Execute-In-Place (XIP) & boot.
SPI Controller Verilog IP Cores
The Master/Slave SPI Controller IP Cores (Verilog Cores DB-SPI-MS-AMBA, DB-SPI-MS-AVLN) contain a parameterized FIFO, Control Unit, & Interrupt Controller to fully off-load the SPI transfer from the processor. The full off-load capabilities target applications with higher performance algorithm requirements or minimal software development plans.
The Master-only SPI Controller IP Cores (Verilog Cores DB-SPI-M-AMBA) have the Master function from the Master/Slave releases, with parameterized FIFO, SPI Master Control Unit, & Interrupt Controller, to fully off-load the SPI transfers from the processor. The Master-only SPI Controller IP offers a smaller VLSI footprint.
The Slave-only SPI Controller IP Cores (Verilog Cores DB-SPI-S-AMBA) have the Slave function from the Master/Slave releases, with parameterized FIFO, SPI Slave Control Unit, & Interrupt Controller, to fully off-load the SPI transfers from the processor. The Slave-only SPI Controller IP offers a smaller VLSI footprint.
SPI XIP Flash Memory Controller Verilog IP Core
The SPI XIP Flash Memory Controller Verilog IP Core (Verilog Core DB-SPI-XIP-FLASH-AMBA) supports Octal/Quad/Dual/Single SPI Flash Memory, with a CPU AMBA Slave interface to the SPI Master function containing SPI Master Control Unit, a parameterized FIFO, & Interrupt Controller, and a second AMBA Slave Interface for Processor Execute-In-Place (XIP).
eSPI Master/Slave Controller Verilog IP Core
The DB-eSPI-SPI-MS-APB Controller IP conforms to the Enhanced Serial Peripheral Interface (eSPI) Specification, satisfying the eSPI Bus Protocol and Transaction and Link Layer requirements. The DB-eSPI-SPI-MS-APB can be programmed to function as an eSPI Master or eSPI Slave, or a SPI Master or SPI Slave. Additional AMBA Interconnects supported are AXI or AHB.
SPI Controller Reference Designs & Evaluations
Digital Blocks offers SPI Controller IP Core reference designs & evaluations that enable you to accelerate the design-in of an SPI Bus within your system.
For ASIC, ASSP, Custom IC design teams, we offer AMBA Interfaces to CPUs in all Master/Slave, Master-only, and Slave-only releases. All SPI Controller IP Cores are available in Verilog RTL. For companies first pursuing FPGA emulation, Digital Blocks support services will fully assist.
To learn more about the SPI Family of IP Cores Digital Blocks offers, including SPI Master/Slave, Master-only and Slave-only IP Cores, SPI Flash Memory Controller IP, as well as Interconnect fabrics for AMBA AXI & AHB & APB & Altera Avalon, please see the IP Cores page or contact Digital Blocks.