I2C Controller/Target Verilog IP Cores

The full core: Controller-Transmitter, Controller-Receiver, Target-Transmitter, and Target-Receiver modes with a parameterized FIFO, FSM Control Unit, and Interrupt Controller that fully off-load the I2C transfer from the processor. Targets applications with higher performance algorithm requirements or minimal software development plans.

• I2C compliant: clock synchronization, arbitration, SCL held low by the target, repeated start, 7/10-bit addressing, general call
• Enhanced SCL / SDA spike filtering and enhanced repeated start
• 13 sources of internal interrupts with masking control
• Optional DMA transfer between the I2C bus and SDRAM / SRAM / FLASH; direct interface to user registers; remote configuration of a Digital Blocks I2C target by an I2C controller
• Optional SMBus support: SMBCLK clock low timeout, SMBDAT minimum data hold time
• Advanced features support queued I2C transactions for higher I2C throughput
• Programmable RX_Sample_Delay to shift-adjust the data read window for enhanced timing closure

The Controller function taken from the Controller/Target releases — parameterized FIFO, I2C Controller Control Unit, and Interrupt Controller — fully off-loading I2C transfers from the processor, at a smaller VLSI footprint.

The Target function taken from the Controller/Target releases — parameterized FIFO, I2C Target Control Unit, and Interrupt Controller — fully off-loading I2C transfers from the processor, at a smaller VLSI footprint.

An I2C Target with an integrated APB, AHB, or AXI manager interface that bridges straight to the AMBA interconnect. For low-footprint ASIC / ASSP designs with no internal configuration registers and no local host CPU — connect it to the interconnect and it transmits and receives I2C payload data to user registers, SRAM, or FIFO.

• Autonomous operation: no local CPU host, no control/status register configuration
• Runs off the bus manager external clock input for a fully synchronous design
• 7- or 10-bit target ID addressing, SCL low wait states, digital SDA/SCL filtering

Target-only cores that use the external SCL as the clock source for the I2C logic, for ICs with low power or low noise requirements and no free-running clock.

• DB-I2C-S-SCL-CLK — configures registers and memory directly, for low noise or low power ICs
• DB-I2C-S-SCL-CLK-APB — interfaces to the CPU in ICs with low power requirements
• 7- or 10-bit addressing, general call, SCL low wait states

Contact Digital Blocks with any additional unique low power I2C Target Controller requirements.

Hs-Mode can be licensed into the Controller/Target, Controller-only, and Target-only cores on any AMBA interface, with full Hs-mode protocol, timing, and electrical compliance to the Hs-mode I2C specification — the highest system-level I2C performance capability on the market.

• 3.4 Mbit/s Hs-Mode transfer on the I2C bus
• Controller FIFO holds blocks of data, with an off-load finite state machine managing the transfers
• Optional DMA controller moves data between the I2C Controller and system memory or registers, in addition to processor access to the FIFO