MIPI IP Cores
Digital Blocks offers MIPI I3C – Inter Integrated Circuit Controller and MIPI DSI-2 – Display Serial interface Controller Verilog IP Cores.
I3C Controller / Target IP Cores — MIPI I3C Basic v1.2, Local CPU Host Interface
The Digital Blocks DB-I3C-BASIC family is compliant with the MIPI I3C Basic v1.2 specification and verified against the MIPI I3C Conformance Test Suite (CTS). Building on the Digital Blocks I2C and SPI families, the SystemVerilog IP cores are offered as Controller+Target (DB-I3C-BASIC-MS), Controller-only (DB-I3C-BASIC-M), and Target-only (DB-I3C-BASIC-S) configurations, each with an AMBA APB or AXI4-Lite host processor interface, supporting the following features:
- Controller (Master), Target (Slave), and combined Controller+Target functions
- Single Data Rate (SDR) mode to 12.5 MHz / 12.5 Mbps, with independent push-pull and open-drain clock dividers
- High Data Rate (HDR) modes: HDR-DDR (25 Mbps) and HDR-BT with Multi-Lane (ML) x1/x2/x4 operation to ~100 Mbps
- Dynamic Address Assignment (ENTDAA, SETNEWDA, RSTDAA) with multi-entry Target address-cache CAM
- In-Band Interrupts (IBI) with Mandatory Data Byte
- Hot-Join capability
- Target Reset Pattern generation and detection, plus HDR Enter/Restart/Exit pattern support (I3C Basic v1.2)
- Broadcast and Direct Common Command Code (CCC) support, including ENEC/DISEC, ENTASx, SETMWL/SETMRL, GETPID/GETBCR/GETDCR, GETSTATUS, GETCAPS, and RSTACT
- Configurable-depth transmit and receive data FIFOs
- AMBA APB or AXI4-Lite host interface with interrupt controller (ISR/IMR/IVR)
- Legacy I2C device support on the I3C bus and Legacy I2C Controller mode
- Glitch/spike filtering and open-drain / push-pull pad control for standard I/O pads
I3C Target-to-AMBA Bridge — Autonomous, No Local CPU Required
The DB-I3C-Target-Bridge family (DB-I3C-Target-Bridge-to-AMBA) is an autonomous MIPI I3C Basic v1.2 Target that bridges the external I3C Controller’s read/write traffic directly onto an AMBA APB or AXI4-Lite bus-master port — requiring no local CPU, not even for configuration:
- Fully autonomous operation: identity (PID, BCR, DCR) set by hardware straps; Dynamic Address assigned over the I3C bus via ENTDAA
- Maps I3C private write/read transfers to AMBA register and memory space with auto-incrementing offset addressing
- Unaligned transfer support with APB4 PSTRB / AXI4-Lite WSTRB byte lanes
- Read prefetch for low-latency I3C read streaming
- External event pin to In-Band Interrupt (IBI) generation, plus optional Hot-Join
- Address-persist mode for resumed reads across I3C frames
- Target Reset Pattern detection with autonomous recovery
MIPI DSI-2
The Digital Blocks MIPI DSI-2 Host Controller IP Core is compliant with the MIPI Display Serial Interface 2, 14-Jan-2016 specification. The Digital Blocks DSI-2 supports the following features:
- DSI Host Controller IP
- DPI or DBI Interface
- DSI Packetizer/Channelizer/Lane Manager
- 1 to 4 Data Lanes
- Display resolutions – QQVGA, QCIF, QVGA, CIF, VGA, WVGA, XGA, FHD, QXGA, QSXGA
- 1 to 4 data lanes
- AMBA APB, AHB, AXI-lite Host Interface