DMA Controller Engines

Digital Blocks DMA Controller IP Cores offer a flexible CPU programming interface and high-performance transfer rates with leading AMBA Interconnects and standard or customized peripheral interfaces. Digital Blocks DMA Controllers are feature-rich with Multi-Channel, Scatter-Gather capability with IP releases targeting CPU AXI/AHB backbone DMA Engines, PCI Express DMA, Network Ethernet DMA, and Peripheral high/low data-rate DMA transfers.

AXI DMA Controller – AXI4 / AXI3 Interconnect

The AXI DMA Controller with Master AXI Interconnect (verilog IP core DB-DMAC-MC-AXI) offers 1-32 Channels with a per channel CPU descriptor-driven interface controlling the data transfer between memory subsystems or between memory and a peripheral. The AXI DMA Controller features Scatter-Gather capability, with per channel Finite State Control and single- or dual-clock FIFOs (parameteried in depth and width), interrupt controller, and optional data parity generator & checker. The AXI Master data Interface scales from 32- to 1024-bits, with programmable data bursts of 1, 4, 8, 16 words (with the smallest data transfer supported is 1 byte), and up to 16 outstanding read requests, and for AXI4, the availability of programmable QoS and longer data burst lengths. The AXI DMA Controller also provides a APB or AXI-lite Slave Interface for CPU access to Control/Status Registers. The DB-DMAC-MC-AXI is tuned as a high-performance DMA Engine, for large and small data block transfers.DB-DMAC-MC-AMBA

AHB DMA Controller – AHB5 Interconnect

The AHB DMA Controller with Master AHB5 Interconnect (verilog IP core DB-DMAC-MC-AHB) offers 1-32 Channels with similar features to the AXI version, with full AHB5 feature support.

AMBA DMA Controller – AXI4 / AXI3 / AHB5 Interconnect

The AMBA DMA Controller configurations includes a mix user selectable AXI4 / AXI3 / AHB5 Master Interconnects (verilog IP core DB-DMAC-MC-AMBA) and offers 1-32 Channels. Please contact Digital Blocks with your requirements.

AXI4 DMA Controller – AXI4-Stream / AXI4 Memory Map Transfers

The DB-DMAC-MC-AXI4-MM-STREAM (verilog IP core DB-DMAC-MC-AXI4-MM-STREAM) is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces. The standard configuration is a two DMA Channel design targeting user requirement of two AXI4-Stream Interfaces, one each Master and Slave, transferring data to/from AXI4 Memory Mapped host memory. Optional configurations contain additional DMA Channel with AXI4-Stream Interface.

AXI4-Stream / AXI Memory Map Address Space Conversion – Interface to DMA Controller

For larger system requiring AXI4-Stream / AXI4 Memory Map Transfers, such as a network interface with many random logic channels streaming and requiring transfers to/from host memory, the following IPs work with the DB-DMAC-MC-AXI4.

Digital Blocks DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE Verilog IP Core works with Digital Blocks AXI DMA Controller to transfer data from an AXI4-Stream Interface peripheral to either memory or another peripheral.

Digital Blocks DB-AXI4-MM-TO-AXI4-STREAM-BRIDGE Verilog IP Core works with Digital Blocks AXI DMA Controller to transfer data from AXI Memory Map Address space memory or another peripheral to an AXI4-Stream Interface peripheral.