DMA Controller Engines
Digital Blocks DMA Controller IP Cores offer a flexible CPU programming interface and high-performance transfer rates with leading AMBA Interconnects and standard or customized peripheral interfaces. Digital Blocks DMA Controllers are feature-rich with Multi-Channel, Scatter-Gather capability with IP releases targeting CPU AXI/AHB backbone DMA Engines, PCI Express DMA, or Peripheral high/low data-rate DMA transfers.
DMA Controller – AXI Interconnect
The DMA Controller with Master AXI Interconnect (verilog IP core DB-DMAC-MC-AXI) offers 1-32 Channels with a per channel CPU descriptor-driven interface or direct programming of registers controlling the data transfer between memory subsystems or between memory and a peripheral. The DMAC features Scatter-Gather capability, with per channel Finite State Control and single- or dual-clock FIFOs (parameteried in depth and width), interrupt controller, and optional data parity generator & checker. The AXI Master data Interface scales from 32- to 256-bits, with programmable data bursts of 1, 4, 8, 16 words (with the smallest data transfer supported is 1 byte), and up to 16 outstanding read requests, and for AXI4, the availability of programmable QoS. The DMAC also provides a APB or AXI-lite or AHB Slave Interface for CPU access to Control/Status Registers. The DB-DMAC-MC-AXI is tuned as a high-performance DMA Engine.
DMA Controller – AHB Interconnect
The DMA Controller with Master AHB Interconnect (verilog IP core DB-DMAC-MC-AHB) offers 1-16 Channels with similar feature to the AXI version, with full AHB feature support but without the additional capabilites the AXI Interconnects offers.