Overview

Digital Blocks low latency IP, UDP, RTP, MPEG-2 TS (Transport Stream) Hardware Protocol Stack Off-load Engine Verilog Cores target network adapter cards with one or more GbE network links.

Digital Blocks Hardware Protocol Stack Verilog Cores target applications requiring much lower latency than a microprocessor running a software protocol stack. Likewise, the Hardware Protocol Stack excels where multiple application data sessions run in parallel with respect to the network, which would certainly overwhelm a microprocessor.

UDP/IP Hard Protocol Stack

Digital Blocks UDP/IP Off-Load Engine (UOE) SoC FPGA/ASIC solutions (Verilog Cores DB-UDP-IP-1GbE, DB-UDP-IP-10GbE, DB-UDP-IP-25GbE, DB-UDP-IP-40GbE, DB-UDP-IP-50GbE, DB-UDP-IP-100GbE) target Aerospace & Defense and Network Client/Server applications. Typically the user application requires either a hardware function in ASIC/FPGA logic to directly access the network to transmit & receive data, or the host processor requires fast access to the network.

RTP Audio/Video Network Streaming

Digital Blocks adds RTP protocol hardware processing to our UDP/IP Off-Load Engine (UOE) SoC FPGA/ASIC solutions (Verilog Core DB-RTP-UDP-IP-AV) and targets Audio/Video Packet Processing such as a RTP/UDP/IP interface to H.264/H.265 CODECs. Both IP Cores contain MAC Layer Pre- & Post-Processing and an ARP Packet Processing for a FPGA or ASIC networking adapter card solution.

MPEG TS Audio/Video Network Streaming

The Digital Blocks adds MPEG Transport Stream (TS) protocol hardware processing to our RTP/UDP/IP Off-Load Engine (Verilog Core DB-RTP-UDP-IP-MPEG-TS) and targets MPEG Transport Stream (TS) processing with RTP/UDP/IP Protocol Hardware Stack, MAC Layer Pre- & Post-Processors, and an ARP Packet Processor targeting high packet throughput or low latency of MPEG Transport of Audio/Video Packets over a Internet Protocol (IP) Network.