Digital Blocks Full-Featured eSPI Controller/Target & SPI Master/Slave IP SystemVerilog Cores
Digital Blocks offers full-featured eSPI Controller/Target SystemVerilog IP cores, available in Controller/Target, Controller-only, and Target-only configurations. We also provide SPI Controller SystemVerilog IP cores supporting Master/Slave, Master-only, and Slave-only modes, along with SPI Flash Memory Controller Verilog IP cores. These SPI Flash Controllers enable efficient CPU access to SPI Flash devices, with optional Execute-In-Place (XIP) support for high-performance embedded applications.
eSPI Controller/Target Verilog IP Core
The DB-eSPI-SPI-MS-APB Controller/Target IP conforms to the Enhanced Serial Peripheral Interface (eSPI) Specification, satisfying the eSPI Bus Protocol and Transaction and Link Layer requirements. The DB-eSPI-SPI-MS-APB can be programmed to function as an eSPI Controller (aka Master) or eSPI Target (aka Slave), or a SPI Master or SPI Slave. Additional AMBA Interconnects supported are AXI or AHB or APB.
The Digital Blocks eSPI Controller/Target IP Core is architected for modern SoC platforms requiring Intel®-style or AMD®-style eSPI connectivity between host processors and embedded controllers, peripherals, or chipset subsystems. The core enables high-performance, low-pin-count system integration while replacing LPC interfaces. Overview Features are as follows:
- Peripheral Channel – Memory-mapped and I/O transactions, posted and non-posted requests
- Virtual Wire Channel – LPC sideband signals and system events
- Out-of-Band (OOB) Channel – Asynchronous messaging and management traffic
- Flash Channel – Host access to SPI flash devices over the eSPI interface
- eSPI Specification 1.5 Compliant
- CRC generation and checking per eSPI specification
- Interrupt generation and status reporting
- Parameterizable TX/RX FIFO depths
- Configurable eSPI data bus widths (Single, Dual, Quad I/O modes)
- AMBA interface options: APB, AHB, AXI4
- Fully synthesizable SystemVerilog RTL
- Optimized for ASIC and FPGA implementation
The architecture provides complete processor offload for eSPI transactions and enables deterministic host-to-peripheral communication in server, embedded controller, networking, and industrial SoC platforms. The core integrates cleanly into AMBA-based system fabrics and supports scalable performance configurations.
SPI Controller Verilog IP Cores
The Master/Slave SPI Controller IP Cores (Verilog Core DB-SPI-MS-AMBA, DB-SPI-MS-AVLN) contain a parameterized FIFO, Control Unit, & Interrupt Controller to fully off-load the SPI transfer from the processor. The full off-load capabilities target applications with higher performance algorithm requirements or minimal software development plans.
The Master-only SPI Controller IP Cores (Verilog Core DB-SPI-M-AMBA) have the Master function from the Master/Slave releases, with parameterized FIFO, SPI Master Control Unit, & Interrupt Controller, to fully off-load the SPI transfers from the processor. The Master-only SPI Controller IP offers a smaller VLSI footprint.
The Slave-only SPI Controller IP Cores (Verilog Core DB-SPI-S-AMBA) have the Slave function from the Master/Slave releases, with parameterized FIFO, SPI Slave Control Unit, & Interrupt Controller, to fully off-load the SPI transfers from the processor. The Slave-only SPI Controller IP offers a smaller VLSI footprint.
The SPI Slave AMBA Bridge (Verilog Core DB-SPI-S-AMBA) supports Slave SPI Bus transfers to/from an AMBA APB, AXI, or AHB Interconnect (also known as SPI2APB, SPI2AXI, SPI2AHB). The SPI Slave Controller receives SPI transactions with regard to an external SPI Master, and completes data transfers by mastering the APB, AXI, or AHB AMBA Interconnect, and typically completes the transfer with respect to user registers or memory. No CPU host is required.
SPI XIP Flash Memory Controller Verilog IP Core
The SPI XIP Flash Memory Controller Verilog IP Core (Verilog Core DB-SPI-XIP-FLASH-AMBA) supports Octal/Quad/Dual/Single SPI Flash Memory, with a CPU AMBA Slave interface to the SPI Master function containing SPI Master Control Unit, a parameterized FIFO, & Interrupt Controller, and a second AMBA Slave Interface for Processor Execute-In-Place (XIP).
SPI Controller Reference Designs & Evaluations
Digital Blocks offers SPI Controller IP Core reference designs & evaluations that enable you to accelerate the design-in of an SPI Bus within your system.
For ASIC, ASSP, Custom IC design teams, we offer AMBA Interfaces to CPUs in all Master/Slave, Master-only, and Slave-only releases. All SPI Controller IP Cores are available in Verilog RTL. For companies first pursuing FPGA emulation, Digital Blocks support services will fully assist.
To learn more about the SPI Family of IP Cores Digital Blocks offers, including SPI & eSPI Master/Slave, Master-only and Slave-only IP Cores, SPI Flash Memory Controller IP, as well as Interconnect fabrics for AMBA AXI, AHB, APB & Altera Avalon, please see the IP Cores page or contact Digital Blocks.