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Welcome to Digital Blocks
Digital Blocks offers semiconductor Intellectual Property (IP) cores for developers with Embedded Processor & Peripherals, High-Speed Networking, Display Controller, Display Link Layer, 2D Graphics, Image Compression, and Audio/Video system requirements.
We offer synthesizable RTL Verilog, SystemVerilog, and VHDL IP cores for System-on-Chip (SoC) ASSP, ASIC, and FPGA designers. At Digital Blocks we are both System Architects and ASIC/FPGA designers. Thus, we provide best-in-clase IP Cores with deep system-level capabilities.
Building on our IP cores, Digital Blocks design services can customize the IP core to your unique requirements, as well as develop higher level system solutions encompassing FPGA, printed circuit board, and software design.
Digital Blocks offers the DB9000 family of programmable Display Controller IP Cores for systems requiring TFT LCD panels in their products. The DB9000 LCD Controller IP supports a wide range of display resolutions and drives an image to the display via on-chip interconnect connecting to Frame Buffer Memory and a Processor.
Digital Blocks offers the DB91000 and DB9200 family of programmable 2D Graphics Hardware Accelerator IP Cores for systems requiring BitBLT and / or 2D Graphics acceleration by hardware rendering. The DB9100 / DB9200 Graphics IP can be added to a system containing the DB9000 LCD Controller IP, with the Graphics IP rendering an image under Processor direction while the LCD Controller IP displays the image.
Digital Blocks Video Signal & Image Processing IP Cores perform a wide range of functions, including NTSC/PAL/SECAM Video Sync Seperator, Color Space Converter, Chroma Resampler, and BT.656 Encoder & Decoder.
Digital Blocks ultra-low latency UDP/IP, TCP/IP, and RTP/UDP/IP with optional MPEG TS Off-load Engine IP Cores target leading-edge network adapter cards with one or more 10/100/1000 MbE or 10/40/100 GbE network links to implement High-Frequency Trading Platforms or Audio/Video Hardware Protocol Stacks. The IP / UDP / RTP / MPEG TS Off-load Engine IP Cores implement in hardware with lower latency and higher packet throughput than a software protocol stack running on a processor.
Digital Blocks Embedded Processor family includes the DB8051, an industry standard microcontroller with standard or customizable peripherals. These include customized PIO, enhanced interrupt capability, & user selected number of UARTs; SPI, CAN, I2C for communications links; a Pulse Width Modulation Unit (PWM) unit; and Error Control (ECC) of Program & Data Memories.
Digital Blocks DB-I2C family of I2C Controllers include Master/Slave, Master only, and Slave only configurations. The I2C Controllers can be configured to support Standard-mode (100 Kbit/s) / Fast-mode (400 Kbit/s) / Fast-mode Plus (1 Mbit/s) / High Speed-mode (3.4 Mbit/s) / Ultra Fast-mode (5 Mbit/s) depending on user system requirements.
Digital Blocks DB-SPI family of SPI Controllers include Master/Slave, Master only, and Slave only configurations. The DB-SPI family shares a similar RTL and programming architecture with the I2C family, and targets Sensor applications.
Digital Blocks DB-DMAC Controller family of DMA Controllers include Mulit-Channels with Descriptor Scatter Gather List data move processing. The DMA Controllers include high-performance AMBA AXI/AHB interconnects, and optional designs supporting user peripherals.
Digital Blocks offers Intel Compatitble 82xx Peripherals IP Cores: The DB8255A Programmable Peripheral Interface; the DB8259 Programmable Interrupt Controller; and the DB8279 Programmable Keyboard / Display Interface.
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