|Welcome to Digital Blocks
Digital Blocks offers semiconductor Intellectual Property (IP) cores for developers
with Embedded Processor & Peripherals, High-Speed Networking, Display
Controller, Display Link Layer, 2D Graphics, Image Compression, and Audio /
Video system requirements.
We offer synthesizable RTL VHDL and Verilog IP cores for System-on-Chip
(SoC) ASSP, ASIC, and FPGA designers.
Programmable Interrupt Controllers
Our Programmable Interrupt Controller IP Core series consists of the DB8259A and DB8259S
interrupt controllers. Both are full-featured equivalents of the industry standard Intel 8259A /
Intersil 82C59A / NEC UPD8259 interrupt controllers. Available in VHDL and Verilog, these
8259 IP cores come with a comprehensive test suite, synthesis scripts, data sheet, and user manual.
We offers these IP Cores as part of its 82xx Peripherals Replacement Program in CPLDs &
Our Display Controller series consists of the DB9000AXI4, DB9000AXI, DB9000AXI-QFHD,
DB9000AXI-DCI, DB9000AHB, DB9000OCP, and the DB9000AVLN LCD Controllers IP Cores
and the DB6845 CRT Controller IP Core.
The DB9000AXI TFT LCD Controller interfaces frame buffer memory and an ARM processor (or
any other high-performance processor) via the AMBA 4.0 AXI bus fabric to TFT LCD panels. The
DB9000AXI contains a 256 / 128 / 64 or 32-bit interface to frame buffer memory, and contains a
programmable option to drive a 1 Port or 2 Port LCD Interface. We optionally offer a LVDS link
layer interface. The DB9000AXI is particularly geared to drive high resolutions panels, including HD
displays. Available in Verilog, the DB9000AXI IP core comes with a comprehensive simulation test
suite, Synopsys Design Constraints for synthesis, and a user manual.
The DB9000AXI4 builds on the AXI version, with the addition of AXI Specfication 2.0 higher burst
lengths (greater than 16 beats per memory request) and Quality of Service (QoS) capabilities.
The DB9000AHB TFT LCD Controller interfaces frame buffer memory and an ARM processor via
the AMBA 2.0 AHB bus fabric to TFT LCD panels. Available in Verilog, the silicon-verified
DB9000AHB IP core comes with a comprehensive test suite, synthesis scripts, data sheet, and user
The DB9000OCP TFT LCD Controller interfaces frame buffer memory and a variety of processors
via the Open Core Protocol Specification 2.2 interface to TFT LCD panels. Available in Verilog and
VHDL, the silicon-verified DB9000OCP IP core comes with a comprehensive test suite, synthesis
scripts, data sheet, and user manual.
The DB9000AVLN TFT LCD Controller interfaces frame buffer memory and an Altera® NIOS® II
processor via the Altera Avalon® Bus to TFT LCD panels. Available in Verilog and VHDL, the
silicon-verified DB9000AVLN IP core comes with a comprehensive test suite, software driver,
synthesis scripts, data sheet, and user manual.
The DB9000AXI-QFHD TFT LCD Controller builds on the AXI4 / AXI3 versions targeting 3840 x
2160 Ultra / Quad Full High Definition (UFHD/QFHD) panels with added streaming video
capabilites. The DB9000AXI-QFHD targets applications in QFHD-TV, Consumer, Education,
Signage, Gaming, Broadcasting, Aerospace / Defense, Simulating & Training, Control Rooms, Tiled
Video Walls, Medical, & Industrial Design.
The DB9000AXI-DCI TFT LCD targets 4K Digital Cinema TFT LCD panels with added features
to meet the Digital Cinema Initiative. The DB9000AXI-DCI targets both 2k and 4K Digital Cinema
Display requirements, and incorporates UFHD / QFHD panel resolutions.
The DB6845 CRT Controller is a full-featured equivalent to the industry standard MC6845.
Available in VHDL, the DB6845 CRT Controller is a customer-proven IP core available with a
comprehensive test suite, synthesis scripts, data sheet, and user manual.
Video Signal & Image Processing
Our Video Signal Processing IP Core consists of the DB1800 NTSC / PAL / SECAM Video Sync
Separator. The DB1800 accepts a composite video signal and outputs horizontal sync, vertical sync,
chroma burst blanking, and field 1 or 2 detection. Available in Verilog, this IP core comes with a
comprehensive test suite, synthesis scripts, data sheet, and user manual.
Programmable Keyboard / Display Interface
Programmable Peripheral Interface
Our Programmable Peripheral Interface IP Core consists of the DB8255A, providing 24 lines of
programmable I/O. The DB8255A is a full-featured equivalent to the industry standard Intel
8255A / 82C55A and Intersil 82C55A. Available in VHDL, this IP core comes with a
comprehensive test suite, synthesis scripts, data sheet, and user manual. We offers this IP Core as
part of its 82xx Peripherals Replacement Program in CPLDs & FPGAs.
Our Programmable Keyboard / Display Interface IP Core consists of the DB8279, which
simultaneously and independently interfaces a keyboard and display to a microprocessor. The
DB8279 is equivalent to the industry standard Intel 8279 / Siemens SAB8279 / NEC UPD8279.
Available in VHDL, this IP core comes with a comprehensive test suite, synthesis scripts, data
sheet, and user manual. We offers this IP Core as part of its 82xx Peripherals Replacement
Program in CPLDs & FPGAs.
|Copyright © Digital Blocks, Inc. 2005-2013. ALL RIGHTS RESERVED
I2C - Inter-Integrated Circuit Controller
|The DB9000AVLN is Qsys / SOPC Builder Ready and AMPP Approved by Altera Corporation.
|The Qsys / SOPC Builder Ready designation by
Altera certifies the DB9000AVLN IP Core contains an
Avalon compatible bus interface, Qsys / SOPC Builder
support files, push-button Qsys / SOPC Builder flow,
software support files, and that the DB9000AVLN is both
software and hardware tested.
|The AMPP Approved Certification designation by
Altera certifies the DB9000AVLN IP Core compiles in the
Altera standard design software flow, is optimized for
the most current Altera device architectures, and
includes good quality documentation.
Digital Blocks' I2C Controller IP Cores offer parameterized FIFOs and Finite State Machine
Control to fully off-load the I2C transfer from the processor. The full off-load capabilities target
applications with high performance algorithm requirements or minimal software overhead
requirements. Digital Blocks' I2C Controllers are available with Master/Slave, Master-only, and
Slave-only feature sets, and in AMBA AXI, AHB, APB as well as Avalon / Qsys bus interfaces.
In addition to interfacing the I2C Bus to a processor, the I2C Controller IP Core can also
interface a set of FPGA / ASIC internal Registers to the I2C Bus. Likewise, the I2C Controller can
interface Memory (SDRAM / SRAM / Flash) external to the FPGA / ASIC to the I2C Bus
The I2C IP Core family offers Hs-mode protocol and timing and electrical compliance to the
Hs-mode I2C specification as a user selectable opton, within the DB-I2C-MS-Hs-Mode release.
With the following features, the DB-I2C-MS-Hs-Mode offers the highest system-level I2C
performance capability on the market: (1) 3.4 Mbit/s Hs-Mode transfer on the I2C Bus: (2)
DB-I2C-MS Controller FIFO to hold blocks of data plus an off-load Finite State Machine to
manage the transfers; (3) streamline DMA controller to move data from the DB-I2C-MS
Controller to System Memory or Registers.
Available in Verilog, the I2C IP Core comes with a comprehensive test suite, synthesis scripts, data
sheet, C software directing I2C Bus transactions, and a user manual. See the Digital Blocks IP
Core page for a full listing of I2C offerings. For information on reference designs, please see the
Digital Blocks I2C IP Core Master / Slave Reference Design page.
Building on our IP cores, Digital Blocks design services can customize the IP core
to your unique requirements, as well as develop higher level system solutions
encompassing FPGA, printed circuit board, and software design.
We offer a Reference Design for the DB9000AVLN, whereby a user can place the DB9000AVLN
LCD Controller in an inexpensive Altera FPGA development kit and connect-up the LCD panel of
their choice. Along with software, the user can start building their application software right away.
Digital Blocks 8051 CPU Core IP Microcontroller ( MCU ) for ASIC / ASSP / FPGA developers
is a 8-bit architecture with 255 instructions complaint with the MCS®51 Instruction Set, and targets
Embedded Control & Communications applications with efficient program space requirements.
Building upon Digital Blocks DB8051C CPU Core -- with its high performance 3 Clocks Per
Instruction (CPI) minimum execution cycle in a small VLSI footprint -- the DDB8051C is based on
Digital Blocks Instruction Overlap Architecture.
The Digital Blocks DB8051C-SP (Standard Peripherals) Microcontroller Verilog IP Core contains
standard 8051 MCU peripherals, including the interrupt controller, UART, two 16-bit timers, and
four 8-bit I/O ports.
The Digital Blocks DB8051C-CP (Configurable Peripherals) Microcontroller Verilog IP Core
contains peripherals pre-customized according to the user's application requirements. Any
combination of 8051 peripherals, including interrupt controller, UART, 16-bit timers, and N-bit I/O
ports, along with SPI, I2C, PWM, DB8279K Keyboard Hardware Controller, as well as enhanced
interrupt capabilities with the DB8259 industry standard interrupt controller for up to 64 interrupts,
can be incorporated into the IP release.
The Digital Blocks DB8051C-FSM contains Digital Blocks DB8051C CPU IP Core with up to 800
I/O for programmable, complex Finite State Machine control applications.
For more information on Digital Blocks DB8051C CPU IP Cores, please visit the Digital Blocks
8051 Microcontroller Verilog IP Cores product page.
BitBLT & 2D Graphics Engines
Our BitBLT & 2D Graphics Engine IP Cores offer hardware acceleration of Bitmap manipulation &
2D Graphics Rendering. The series consists of the DB9100AXI4, DB9100AXI, DB9100AHB, and
DB9100AVLN Verilog IP Cores. The DB9100 family of BitBLT & 2D Graphics IP complement the
DB9000 family of TFT LCD Controller IP.
High-Frequency Trading / High-Speed Networking
Digital Blocks DB-UDP-IP-HFT ultra-low latency IP/UDP Off-load Engine (UOE) IP SoC Core
targets leading-edge network adapter cards with one or more 10 / 40 GbE network links to
implement High-Frequency Trading Platforms. For more information, please visit the Digital Blocks
High-Frequency Trading IP Cores product page.
Low-Latency RTP/UDP/IP Protocol Hardware Stack for Audio/Video Applications
The Digital Blocks DB-RTP-UDP-IP-AV IP Core is a RTP/UDP/IP Protocol Hardware Stack with
MAC Layer Pre- & Post-Processors and an ARP Packet Processor targeting low latency, full off-load
from a processor, of Audio/Video Packet Processing. The DB-RTP-UDP-IP-AV is a Verilog SoC IP
Core targeting Xilinx/Altera/Lattice FPGAs and ASIC/ASSP devices.