Digital Blocks is a leading developer of silicon-proven semiconductor Intellectually Property (IP) cores for developers requiring best-in-class IP for Embedded Processors, I2C/SPI/DMA Peripherals, TFT LCD/OLED Display Controllers & Processors, 2D Graphics Hardware Accelerator Engines, LVDS Display Link Layer Drivers, Video Signal & Image Processing, and Low-Latency TCP/UDP/RTP Hardware Protocol Stacks.
We offer synthesizable RTL Verilog, SystemVerilog, and VHDL IP Cores for System-on-Chip (SoC) ASSP, ASIC, and FPGA designers. At Digital Blocks we are both System Architects and ASIC/FPGA designers. Thus, we provide IP Cores with deep system-level capabilities.
Building on our IP cores, Digital Blocks design services can customize the IP core to your unique requirements, as well as develop higher level system solutions encompassing FPGA, printed circuit board, and software design.
TFT LCD Display Controllers
Digital Blocks offers the DB9000 family of programmable Display Controller IP Cores for systems requiring TFT LCD panels in their products. The DB9000 LCD Controller IP supports a wide range of display resolutions and drives an image to the display via on-chip interconnect connecting to Frame Buffer Memory and a Processor.
2D Graphics Hardware Accelerator Engines
Digital Blocks offers the DB91000 and DB9200 family of programmable 2D Graphics Hardware Accelerator IP Cores for systems requiring BitBLT and / or 2D Graphics acceleration by hardware rendering.
Embedded Processors & Peripherals
Digital Blocks offers best-in-class 8/16-bit MCU, ARM AMBA I2C, SPI, QSPI Flash, UART, PWM, and DMA Controller Peripherals, and Intel Compatible 8255/8259/8279 Peripherals IP Cores.
Video Signal and Image Processing
Digital Blocks Video Signal & Image Processing IP Cores perform a wide range of functions, including NTSC/PAL/SECAM Video Sync Separator, Color Space Converter, Chroma Resampler, and BT.656 Encoder & Decoder.
Low-Latency, High-Speed Networking
Digital Blocks ultra-low latency UDP/IP, TCP/IP, and RTP/UDP/IP with optional MPEG TS Off-load Engine IP Cores target leading-edge network adapter cards with one or more 10/100/1000 MbE or 10/40/100 GbE network links to implement low-latency interface to network